The present invention relates to a process for producing a charge storage capacitor for a dRAM (dynamic random access memory), which is minute and yet has a large capacity.
There has been a 4-fold increase in packing density of dRAM's in the last three years. The main production item of this type of memory has already been shifted from 64K-devices to 256K-devices, and the mass-production of 1M-bit dRAM's will soon be put into practice. This large integration of dRAM's has been accomplished by reduction in device size which is known as the "scaling rule". However, a decrease in storage capacitance which results from the reduction in device size leads to drawbacks such as a lowering of S/N ratio and undesirable signal reverse due to .alpha.-particles, which gives rise to a serious problem in terms of reliability. In view of these circumstances, new types of capacitor cells which are designated to increase the storage capacitance are expected to replace the conventional planar type capacitor cell, such as a trench capacitor cell which utilizes the side wall of a trench provided in a substrate and a stacked capacitor cell which has a stacked capacitor section [see, "Novel high density, Stacked capacitor MOS RAM" by Koyanagi, Sumami, Hashimoto and Ashikawa in IEEE Int, Electron Devices Meeting Tech, Dig. pp. 348-351, December (1978)]. Among these improved capacitor cells, the stacked capacitor cell has become of major interest as one which has a capacitor structure that meets the future demand for further reduction in the device size because, unlike the trench capacitor cell, the stacked capacitor cell needs no advanced technique to provide a fine or minute trench in a substrate.
FIG. 1 is a sectional view of a dRAM having a conventional stacked capacitor cell. The process for producing this type of dRAM will briefly be explained below. First, an element isolation oxide 2 is grown on a single crystal substrate 1, and an oxide 3 which defines a gate oxide of a transistor is then grown. Impurity-containing polycrystalline silicon 4 is deposited to provide a gate electrode and processed. Thereafter, a source 5 and a drain 6 are formed by self-alignment process using ion implantation or the like. Then, to form a charge storage capacitor section, impurity-containing polycrystalline silicon 8 is deposited on a region above the drain. At this time, the polycrystalline silicon 8 is also formed on the gate electrode 4 and the element isolation oxide 2. Therefore, it is possible to increase the area of the capacitor section as compared with the conventional planar capacitor cell structure which utilizes the plane of the substrate alone. It should be noted that the gate electrode 4 is covered with an insulator 7 such as an oxide. As oxide 9 is then formed on the polycrystalline silicon 8, formed as described above, so as to provide an insulator for a capacitor cell. A conductor 10 is deposited on the oxide 9 to complete a capacitor cell. It should be noted that the reference numeral 11 denotes a protection film, 12 a word line electrode, 13 a data line electrode, and 14 a plate electrode.
In the above-described conventional stacked capacitor cell, however, the surface of the first-level polycrystalline silicon 8 alone is utilized, as shown in FIG. 1. Therefore, it is not necessarily possible to obtain a satisfactorily large capacitance, particularly in a cell which is reduced in device size to a great extent.